There is currently much interest in providing digital electronic circuits with an internal capability of testing themselves (built-in self-test). One built-in self-test technique which has shown much promise for digital electronic circuits is that of pseudo-exhaustive self-testing, which is described and claimed in co-pending U.S. patent application Ser. No. 484,336, filed on Feb. 26, 1990, in the names of J. A. Malleo-Roach et al. and assigned to AT&T Bell Laboratories (herein incorporated by reference). As described in the Malleo-Roach application, pseudo-exhaustive testing of an electronic circuit is carried out by first partitioning the circuit into individual sub-circuits, hereinafter referred to as "cones," each having only one output and no more than a predetermined number of inputs.
In addition to partitioning the circuit, a test generator is added to the circuit under test for generating a set of vertical canonical vectors at its output. A separate subset of the canonical vectors is then assigned to the inputs of each cone such that the vectors in each subset are independent of each other to assure exhaustive testing of the cone.
Upon receipt of a test vector at its inputs, each cone generates a response signal bit. The response signal bits from the cones are compacted (compressed) to yield a reduced length stream of bits indicative of the response of the cones, which is determinative of whether the circuit contains any faults. For a further description of the above-described pseudo-exhaustive self-testing technique, reference should be had to the Malleo-Roach et al. application, Ser. No. 484,336.
Compaction of the response data has traditionally been accomplished by exclusively OR'ing the response bit produced at each observation point (the output of a cone) with the response bit produced by an upstream cone at an earlier interval. To carry out compaction of the response signals in this manner, Multiple Input Shift Registers (MISRs) have been employed. A typical MISR comprises a plurality of MISR cells daisy-chained together to form a circle, with each cell containing an exclusive OR (XOR) gate having a first input supplied with the response bit from an observation point, such as the output of a cone, and a second input supplied with the output of an upstream MISR cell. Each MISR cell also comprises a flip-flop whose input is supplied with the output of the XOR gate of the cell and whose output is supplied to an input of the XOR gate of a downstream MISR cell. At the completion of testing, the pattern of bits (referred to as a "signature") stored by the MISR will be indicative of the operation of the circuit. By comparing the MISR signature to that obtained when the circuit is fault-free, a determination can be made as to whether the circuit under test has any defects (faults).
The disadvantage associated with the use of MISRs for compacting response signals from a circuit under test is that such devices are not "cost-effective" from the standpoint that each MISR cell generally requires a large number of grids (gates) for its implementation. In the case of a large circuit comprised of many cones, the number of MISR cells will correspondingly be high, imposing a large, undesirable overhead penalty.
Thus, there is a need for a technique for compacting response data which is efficient in terms of the number of elements required for the task.